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| CY2314ANZ 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Features Functional Description The CY2314ANZ is a 3.3V buffer designed to distribute high speed clocks in desktop PC applications. The part has 14 outputs, 12 of which can be used to drive up to three SDRAM DIMMs. The remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz. The CY2314ANZ also includes a serial interface which can enable or disable each output clock. On power up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE. One input to 14 output buffer or driver Supports up to three SDRAM DIMMs Two additional outputs for feedback Serial interface for output control Low skew outputs Up to 100 MHz operation Multiple VDD and VSS pins for noise reduction Dedicated OE pin for testing Low EMI outputs 28-pin SOIC (300-mil) package 3.3V operation Logic Block Diagram BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 Serial Interface Decoding SCLOCK SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDATA OE Cypress Semiconductor Corporation Document #: 38-07143 Rev. *B * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised November 10, 2008 [+] Feedback CY2314ANZ Pin Configuration Figure 1. 28-Pin SOIC Top View VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN SDRAM4 SDRAM5 SDRAM12 VDDIIC SDATA V DD SDRAM11 SDRAM10 V SS V DD SDRAM9 SDRAM8 V SS OE SDRAM7 SDRAM6 SDRAM13 V SSIIC SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Device Functionality OE 0 1 SDRAM [0-13] High-Z 1 x BUF_IN Serial Configuration Map The serial bits are read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Table 2. Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 27 26 23 22 --19 18 Description SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved, Drive to 0 Reserved, Drive to 0 SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) Reserved and unused bits should be programmed to "0" Serial interface address for the CY2314ANZ is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---- Table 1. Byte 0: SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enabled Bit Pin # Description SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Reserved, Drive to 0 Reserved, Drive to 0 SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Bit 7 11 Bit 6 10 Bit 5 -Bit 4 -Bit 3 7 Bit 2 6 Bit 1 3 Bit 0 2 Table 3. Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 17 12 ------Description SDRAM13 (Active/Inactive) SDRAM12 (Active/Inactive) Reserved, Drive to 0 Reserved, Drive to 0 Reserved, Drive to 0 Reserved, Drive to 0 Reserved, Drive to 0 Reserved, Drive to 0 Document #: 38-07143 Rev. *B Page 2 of 8 [+] Feedback CY2314ANZ Maximum Ratings Supply Voltage to Ground Potential................-0.5V to +7.0V DC Input Voltage (Except BUF_IN) ....... -0.5V to VDD + 0.5V DC Input Voltage (BUF_IN) ............................-0.5V to +7.0V Storage Temperature ................................. -65C to +150C Junction Temperature................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions [1] Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min 3.135 0 Max 3.465 70 30 7 50 Unit V C pF pF ms Electrical Characteristics Over the Operating Range Parameter VIL VILiic VIH IIL IIL IIH VOL VOH IDD IDD IDD IDD IDDS Description Input LOW Voltage[2] Input LOW Voltage Input HIGH Voltage[2] Input LOW Current (BUF_IN input) Input LOW Current (Except BUF_IN Pin) Input HIGH Current Output LOW Output HIGH Supply Supply Supply Voltage[3] Voltage[3] VIN = 0V VIN = 0V VIN = VDD IOL = 25 mA IOH = -36 mA Unloaded outputs, 100 MHz Loaded outputs, 100 MHz Unloaded outputs, 66.67 MHz Loaded outputs, 66.67 MHz BUF_IN=VDD or VSS All other inputs at VDD 2.4 200 290 150 185 500 -10 Test Conditions Except serial interface pins For serial interface pins only 2.0 -10 10 100 10 0.4 Min Max 0.8 0.7 Unit V V V A A A V V mA mA mA mA A Current[3] Current[3] Current[3] Supply Current[3] Supply Current Notes 1. Electrical parameters are guaranteed under the operating conditions specified. 2. BUF_IN input has a threshold voltage of VDD/2. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07143 Rev. *B Page 3 of 8 [+] Feedback CY2314ANZ Switching Characteristics[4] Over the Operating Range Parameter Duty Cycle t3 t4 t5 t6 t7 t8 t9 Name Maximum Operating Frequency [3, 5] Test Conditions Measured at 1.5V Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V [3] Min 45.0 0.9 0.9 -250 1.0 1.0 1.0 1.0 Typ 50.0 1.5 1.5 3.5 3.5 5 20 Max 100 55.0 4.0 4.0 +250 5.0 5.0 12 30 Unit MHz % V/ns V/ns ps ns ns ns ns = t2 / t1 [3] Rising Edge Rate Falling Edge Rate[3] Output to Output Skew SDRAM Buffer LH Propogation Delay[3] SDRAM Buffer HL Propogation Delay[3] SDRAM Buffer Enable Delay[3] SDRAM Buffer Disable Delay[3] All outputs equally loaded Input edge greater than 1 V/ns Input edge greater than 1 V/ns Input edge greater than 1 V/ns Input edge greater than 1 V/ns Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 1.5V 1.5V 1.5V Figure 3. All Outputs Rise/Fall Time OUTPUT 2.4V 0.4V t3 2.4V 0.4V t4 3.3V 0V Figure 4. Output-Output Skew OUTPUT 1.5V OUTPUT t5 1.5V Notes 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate of the input clock is greater than 1 V/ns. Document #: 38-07143 Rev. *B Page 4 of 8 [+] Feedback CY2314ANZ Switching Waveforms (continued) Figure 5. SDRAM Buffer LH and HL Propagataion Delay INPUT OUTPUT t6 t7 Figure 6. SDRAM Buffer Enable and Disable Times OE Three-State OUTPUTS t8 Active t9 Test Circuit VDD 0.1 F OUTPUTS CLK out CLOAD GND Document #: 38-07143 Rev. *B Page 5 of 8 [+] Feedback CY2314ANZ Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Figure 7. Application Circuit Rs CPUCLK PCICLK USBCLK REF APIC BUF_IN Rs SDATA SCLK V DD 3.3V Ct V DD SDATA SCLK SDRAM(0-13) SDRAM(0-13) * CY2280 48 Pin SSOP (or CY2281 or CY2282) Cd 0.1uF VSS CY 2314 28 Pin SOIC * This Frequency Synthesizer is used to generate CPU, PCI, USB, REF, and APIC Clocks Cd = DECOUPLING CAPACITORS Ct = OPTIONAL EMI REDUCING CAPACITORS Rs = SERIES TERMINATING RESISTORS Recommendation Surface mount, low ESR,and ceramic capacitors must be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout Footprints must be laid out for optional EMI reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. A ferrite bead may be used to isolate the board VDD from the clock generator VDD island. Ensure that the ferrite bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Refer to the application note Layout and Termination Techniques for Cypress Clock Generators for more details. If a ferrite bead is used, a 10 F to 22 F tantalum bypass capacitor should be placed close to the ferrite bead. This capacitor prevents power supply droop during current surges. Ordering Information Ordering Code Pb-Free CY2314ANZSXC-1 CY2314ANZSXC-1T SZ283 SZ283 28-Pin SOIC 28-Pin SOIC - Tape and Reel Commercial Commercial Package Name Package Type Operating Range Document #: 38-07143 Rev. *B Page 6 of 8 [+] Feedback CY2314ANZ Package Diagram Figure 8. 28-Pin (300-Mil) Molded SOIC SZ283 51-85026-A Document #: 38-07143 Rev. *B Page 7 of 8 [+] Feedback CY2314ANZ Document History Page Document Title: CY2314ANZ 14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Document Number: 38-07143 Rev. ** *A *B ECN No. 110252 121830 2606695 Orig. of Change DSG RBI KVM/PYRS Submission Description of Change Date 11/18/01 12/14/02 11/13/08 Change from Spec number: 38-00687 to 38-07143 Power up requirements added to Operating Conditions Information Update Ordering Information Table: Remove CY2314ANZSC-1 Add Pb-free devices CY2314ANZSXC-1 and CY2314ANZSXC-1T Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07143 Rev. *B Revised November 10, 2008 Page 8 of 8 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback |
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